The present invention relates generally to integrated circuits, and more specifically, to a method and system for simultaneously reading data from a plurality of indexed arrays.
An Integrated Circuit (IC) is a collection of a plurality of electronic circuits that are connected together on a miniature semiconductor chip. Some examples of ICs are microprocessors, microcontrollers, digital memory chips, and the like. Miniaturization results in enhanced performance of the ICs, since small and closely packed circuits consume less power. Further, these circuits have a faster speed due to shorter paths traced by the circuit connections. Typically, speedier circuits are desirable in memory, to execute instructions at a higher speed, resulting in a faster computational rate.
Generally, memory is organized in the form of memory arrays. Typically, circuits for memory access are designed, based on the array structure of memory. The arrays constituting a memory have indexed memory locations that can store data. Typically, circuits for memory access are multiplexing circuits. These multiplexing circuits can selectively access an indexed memory location, based on a value, over a selector line. Simultaneously accessing memory locations from multiple arrays can result in faster memory access.
Currently, there exist one or more methods for simultaneously accessing memory locations from multiple arrays. One such method uses selector lines to select and access a particular memory location. These selector lines are driven by buffer elements, which improve the strength of the signals on the selector lines. The signals on the selector lines drive the multiplexing circuits, which are arranged hierarchically in one or more levels. Each level comprises one or more multiplexers. An output is selected at each level of hierarchy of the multiplexers, based on the signal value of the input selector signals.
Due to the selections made at each level, a higher hierarchical level has less number of inputs as compared to a lower hierarchical level. This results in the use of fewer multiplexers at the higher hierarchical level. Further, the number of multiplexers driven by each selector line varies because each hierarchical level is driven by a different selector line. Due to this arrangement, selector lines that drive a greater number of multiplexers have a larger critical path. This increases the time taken to access the memory. Further, the number of buffer elements required to drive the selector lines at each hierarchical level also varies, resulting in a large chip area being occupied by the buffer elements.
Therefore, in light of the above, it is desirable to reduce the memory access time and decrease the chip area. Consequently, there is a need for a method and system that enables simultaneous reading of data from multiple arrays in comparatively reduced time. Further, the method and system should also utilize less chip area as compared to existing methods.